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| ICX054AL 1/3-inch CCD Image Sensor for EIA B/W Camera For the availability of this product, please contact the sales office. Description The ICX054AL is an interline CCD solid-state image sensor suitable for EIA 1/3-inch B/W video cameras. High sensitivity is achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip features a field period readout system, and an electronic shutter with variable chargestorage time. Features * High sensitivity (+3dB compare with ICX044BLA) and low dark current * Continuous variable-speed shutter 1/60s (Typ.), 1/100s to 1/10000s * Low smear * Excellent antiblooming characteristics * Horizontal register: 5V drive * Reset gate: 5V drive Device Structure * Optical size: * Number of effective pixels: * Number of total pixels: * Interline CCD image sensor * Chip size: * Unit cell size: * Optical black: * Number of dummy bits: * Substrate material: 16 pin DIP (Plastic) Pin 1 1 V 12 2 Pin 9 H 25 1/3-inch format 510 (H) x 492 (V) approx. 250K pixels 537 (H) x 505 (V) approx. 270K pixels Optical black position (Top View) 6.00mm (H) x 4.96mm (V) 9.6m (H) x 7.5m (V) Horizontal (H) direction: Front 2 pixels, Rear 25 pixels Vertical (V) direction: Front 12 pixels, Rear 1 pixel Horizontal 16 Vertical 1 (even field only) Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E92705E66-ST ICX054AL VOUT VGG VSS GND V2 8 7 6 5 V1 V3 4 3 2 Vertical register Note Horizontal register Note) 9 10 11 12 13 14 15 16 : Photo sensor GND SUB Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol V4 V3 V2 V1 GND VGG VSS VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Output amplifier gate bias Output amplifier source Signal output VDD Pin No. 9 10 11 12 13 14 15 16 H1 Symbol VDD GND SUB VL RG NC H1 H2 H2 VL RG NC V4 1 Block Diagram and Pin Configuration (Top View) Description Output amplifier drain supply GND Substrate (Overflow drain) Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock Absolute Maximum Ratings Item Substrate voltage SUB - GND Supply voltage VDD, VOUT, VSS - GND VDD, VOUT, VSS - SUB V1, V2, V3, V4 - GND V1, V2, V3, V4 - SUB Ratings -0.3 to +55 -0.3 to +18 -55 to +10 -15 to +20 to +10 to +15 to +17 -17 to +17 -10 to +15 -55 to +10 -65 to +0.3 -0.3 to +30 -0.3 to +24 -0.3 to +20 -30 to +80 -10 to +60 -2- Unit V V V V V V V V V V V V V V C C 1 Remarks Vertical clock input voltage Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H1, H2 - V4 H1, H2, RG, VGG - GND H1, H2, RG, VGG - SUB VL - SUB V1, V2, V3, V4, VDD, VOUT - VL RG - VL VGG, Vss, H1, H2 - VL Storage temperature Operating temperature 1 +27V (Max.) when clock width < 10s, clock duty factor < 0.1%. ICX054AL Bias Conditions Item Output amplifier drain voltage Output amplifier gate voltage Output amplifier source Substrate voltage adjustment range Fluctuation range after substrate voltage adjustment Reset gate clock voltage adjustment range Fluctuation range after reset gate clock voltage adjustment Protective transistor bias Symbol VDD VGG VSS VSUB VSUB VRGL VRGL VL Min. 14.55 1.75 Typ. 15.0 2.0 Max. 15.45 2.25 Unit V V 5% V % V % 1 1 Remarks Grounded with 680 resistor 9.0 -3 1.0 -3 2 18.5 +3 4.0 +3 DC Characteristics Item Output amplifier drain current Input current Input current Symbol IDD IIN1 IIN2 Min. Typ. 3 1 10 Max. Unit mA A A 3 4 Remarks 1 Indications of substrate voltage (VSUB) * reset gate clock voltage (VRGL) setting value. The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image sensor by a special code. Adjust substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the indicated voltage. Fluctuation range after adjustment is 3%. VSUB code VRGL code one character indication one character indication VRGL code VSUB code Code and optimal setting correspond to each other as follows. 1 2 3 4 5 6 7 VRGL code Optimal setting VSUB code Optimal setting 1.0 1.5 2.0 2.5 3.0 3.5 4.0 E f G h J K L m N P Q R S T U V W X Y Z 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 ICX054AL Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage |VVH1 - VVH2| VVH3 - VVH VVH4 - VVH VVHH VVHL VVLH VVLL Horizontal transfer clock voltage Reset gate clock voltage Substrate clock voltage VH VHL VRG VRGLH - VRGLL VSUB 22.5 23.5 4.75 -0.05 4.5 5.0 0 5.0 -0.25 -0.25 Min. 14.55 -0.05 -0.2 -9.0 7.8 Typ. 15.0 0 0 -8.5 8.5 Max. 15.45 0.05 0.05 -8.0 9.05 0.1 0.1 0.1 0.5 0.5 0.5 0.5 5.25 0.05 5.5 0.8 24.5 Unit V V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 2 3 3 4 4 5 1 Low-level coupling High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL3 + VVL4) /2 VV = VVHn - VVLn (n = 1 to 4) VVH = (VVH1+VVH2) /2 Remarks 1 The reset gate clock voltage need not be adjusted when reset gate clock is driven when the specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image sensor has not significance. Item Reset gate clock voltage Symbol VRGL VRG Min. -0.2 8.5 Typ. 0 9.0 Max. 0.2 9.5 Unit V V Waveform diagram 4 4 Remarks -4- ICX054AL Clock Equivalent Circuit Constant Item Capacitance between vertical transfer clock and GND Symbol CV1, CV3 CV2, CV4 CV12, CV34 Capacitance between vertical transfer clocks CV23, CV41 CV13 CV24 Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor Horizontal transfer clock series resistor Reset gate clock series resistor V1 CV12 Min. Typ. 1500 820 470 230 150 230 47 47 5 320 51 100 15 10 40 Max. Unit pF pF pF pF pF pF pF pF pF pF Remarks CH1, CH2 CHH CRG CSUB R1, R3 R2, R4 RGND RH RRG V2 R1 R2 RH H1 RH H2 CHH CV23 CH1 CH2 CV13 CV1 CV41 CV24 CV4 R4 CV2 RGND CV34 CV3 R3 V4 V3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit RRG RG CRG Reset gate clock equivalent circuit -5- ICX054AL Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II M M 2 tf 0V VVT 10% 0% tr twh (2) Vertical transfer clock waveform V1 V3 VVH1 VVHH VVH VVHL VVHH VVHH VVHL VVHL VVH3 VVHH VVHL VVH VVL1 VVLH VVL3 VVLL VVL VVLH VVL VVLL V2 V4 VVHH VVHH VVH VVHL VVH VVHH VVHH VVH2 VVHL VVHL VVH4 VVHL VVL2 VVLH VVLH VVLL VVL VVL4 VVLL VVL -6- ICX054AL (3) Horizontal transfer clock waveform tr twh tf 90% VH 10% VHL twl (4) Reset gate clock waveform tr twh tf VRGH twl Point A RG waveform VRGLH VRGL VRGLL VRG VRGL + 0.5V H1 waveform 10% VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VRG = VRGH - VRGL -7- ICX054AL (5) Substrate clock waveform 100% 90% M VSUB 10% 0% M 2 tf VSUB tr twh Clock Switching Characteristics Item Readout clock Vertical transfer clock Horizontal transfer clock Horizontal transfer clock Horizontal transfer clock Reset gate clock Substrate clock Symbol VT V1, V2, V3, V4 H H1 H2 RG SUB 11 15 75 37 41 5.6 5.6 79 38 42 12 0.012 0.012 6.5 0.5 15 twh twl tr tf Unit Remarks s During readout Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.3 2.5 0.5 0.015 2 10 0.012 0.012 4.5 0.5 0.5 0.25 s 1 15 ns During imaging s During parallelserial s conversion ns s During drain charge 1.5 2.0 1 When vertical transfer clock driver CXD1250 is used. 2 tf tr - 2ns -8- ICX054AL Image Sensor Characteristics Item Sensitivity Saturation signal Smear Video signal shading Dark signal Dark signal shading Flicker Lag Symbol S Vsat Sm SH Vdt Vdt F Lag Min. 470 700 0.005 0.007 20 25 2 1 2 0.5 Typ. 560 Max. Unit mV mV % % % mV mV % % Measurement method 1 2 3 4 4 5 6 7 8 (Ta = 25C) Remarks Ta = 60C Zone 0, I Zone 0 to II' Ta = 60C Ta = 60C Zone Definition of Video Signal Shading 510 (H) 10 8 9 H 8 V 10 H 8 492 (V) Zone 0, I Zone II, II' V 10 10 Ignored region Effective pixel region -9- ICX054AL Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the substrate voltage and the reset gate clock voltage are set to the values indicated on the device, and the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [A] in the drive circuit example is used. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs x 250 60 [mV] 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with average value of the signal output, 200mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value VSm [mV] of the signal output and substitute the value into the following formula. Sm = 1 VSm 1 x x x 100 [%] (1/10V method conversion value) 200 500 10 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax - Vmin)/200 x 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. - 10 - ICX054AL 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (Vf [mV]). Then substitute the value into the following formula. F = (Vf/200) x 100 [%] 8. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/200) x 100 [%] FLD SG1 Light Strobe light timing Signal output 200mV Output Vlag (lag) - 11 - Drive Circuit 2SC2785 x 3 0.1 1/35V 1/35V 27k 0.1 1/35V 3.3/16V 22/16V 27k 180k 680 47/6.3V 39k 15k 0.1 -8.5V 100k 56k 270k 15k 47k 15V 5V 20 19 18 17 16 15 14 12 11 1 2 3 45 22/20V 67 8 100 1/6.3V 10/20k 1 XSUB XV2 2 3 XV1 4 XSG1 5 6 13 CXD1250 XV3 XSG2 7 8 XV4 9 V3 V4 V2 V1 VGG VSS GND VOUT H1 NC GND H2 H2 16 15 14 13 12 11 10 RG VL SUB 9 1500p 0.01 3.3/20V 1M H1 2SA1175 100k 10k 10/16V 47k 0.1 0.01 ICX054AL RG VDD - 12 - ICX054 (BOTTOM VIEW) 22 /10V 10 [A] CCD OUT 3.9k 2SK523 ICX054AL Spectral Sensitivity Characteristics (Includes lens characteristics, excludes light source characteristics) 1.0 0.9 0.8 0.7 Relative Response 0.6 0.5 0.4 0.3 0.2 0.1 0.0 400 500 600 700 Wave Length [nm] 800 900 1000 Sensor Readout Clock Timing Chart HD V1 2.5 V2 Odd Field V3 V4 38.1 1.2 1.5 2.5 2.0 0.3 V1 V2 Even Field V3 V4 Unit: s - 13 - Drive Timing Chart (Vertical sync) FLD VD BLK HD 10 15 20 265 270 520 260 275 SG1 SG2 V1 V2 V3 V4 492 491 CCD 246 135 246 135 OUT 525 1 2 3 4 5 492 491 246 135 2468 1357 CLP1 280 - 14 - ICX054AL Drive Timing Chart (Horizontal sync) HD BLK H1 1 2 3 5 H2 20 25 10 15 16 1 2 1 2 3 5 10 5 10 500 RG XSHP - 15 - XSHD V1 V2 V3 V4 CLP1 SUB 505 510 1 2 3 15 ICX054AL ICX054AL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection a) Operate in clean environments (around class 1000 is appropriate). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Do not expose to strong light (sun rays) for long periods. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. - 16 - Package Outline Unit: mm 16pin DIP (450mil) A 0 to 9 6.1 9 16 D ~ 2.5 C 11.43 8.4 5.7 V 2-R0.5 ~ 2.5 H 9.5 11.4 0.1 0.5 B' 3.1 0.3 M 1.27 3.5 0.3 - 17 - 1.2 2.5 1. "A" is the center of the effective image area. 3.35 0.15 9.2 ~ 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 3. The bottom "C" of the package, and the top of the cover glass "D" are the height reference. 4. The center of the effective image area relative to "B" and "B'" is (H, V) = (6.1, 5.7) 0.15mm. 5. The rotation angle of the effective image area relative to H and V is 1. 6. The height from the bottom "C" to the effective image area is 1.41 0.10mm. The height from the top of the cover glass "D" to the effective image area is 1.94 0.15mm. 7. The tilt of the effective image area relative to the bottom "C" is less than 50m. The tilt of the effective image area relative to the top "D" of the cover glass is less than 50m. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. ICX054AL 0.69 1.27 0.46 0.3 (For the first pin only) PACKAGE STRUCTURE PACKAGE MATERIAL Plastic LEAD TREATMENT GOLD PLATING LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.9g 0.25 1.2 11.6 10.3 12.2 0.1 8 1 2.5 B |
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